GB/T 37979-2019 in English
VALIDSafe rule of VHDL for programmable logic device software
- Issued on:2019-08-30
- Implemented on:2020-03-01
- File Format:PDF
- Delivery:Via email within 5 business days
$612.00
| Standard No: | GB/T 37979-2019 |
| Document status: | VALID |
| Title in English: | Safe rule of VHDL for programmable logic device software |
| Title in Chinese: | 可编程逻辑器件软件VHDL编程安全要求 |
| Language: | English |
| File Format: | Electronic (PDF) |
| Delivery: | Via email within 5 business days |
| Issued on: | 2019-08-30 |
| Implemented on: | 2020-03-01 |
| ICS Classification: | 35.080-Software development and system documentation |
| Chinese Classification: | L77-Software engineering |
| Professional Classification: | GB-National Standard |
| Related Topics: | programming
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《GB/T 37979-2019可编程逻辑器件软件VHDL编程安全要求》由TC28(全国信息技术标准化技术委员会)归口,主管部门为国家标准化管理委员会。
Introduction
Analysis of Core Safety Requirements
| Safety Category | Key Requirements | Typical Risks |
|---|---|---|
| Instantiation Class | Must use name mapping, input ports must not be left floating | Reduced readability, undefined behavior |
| Clock Class | Prohibit clock re-convergence, avoid gated clock | Timing conflict, metastable state |
| State Machine Class | Must handle invalid states, three-segment structure is recommended | Deadlock risk, logical error |
Key technology implementation points
1. Port instantiation specifications
The standard 5.1.1 clearly stipulates that the name mapping method must be used:
reset_filter_inst: reset_filter port map( reset_in => reset_in, clk => clk, reset_out => reset_out );
The position mapping method is prohibited to avoid maintenance difficulties.
2. Clock domain processing solution
According to the requirements of 5.9.6, cross-clock domain signals must be synchronized:
process(clk) begin if rising_edge(clk) then async_reg1 <= async_signal; async_reg2 <= async_reg1; end if; end process;
Two-level register synchronization can effectively reduce the risk of metastable state.
3. State machine design specifications
5.11.4Recommended three-stage state machine structure:
- State register migration process
- Combinational logic state transfer process
- Synchronous output process
Requires the safety coding attribute: attribute syn_encoding of current_state: signal is "safe, gray";

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