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Database: 365,228(8 Aug 2026)
synchronous dynamic random access memory double data rate circuit measuring methods ddr3 sdram ddr3 sdramd indication signals rubber package multi-link suspension
GB/T 36474-2018 in English

GB/T 36474-2018 in English

VALID

Semiconductor integrated circuit—Measuring methods for double data rate 3 synchronous dynamic random access memory(DDR3 SDRAM)

  • Issued on:2018-06-07
  • Implemented on:2019-01-01
  • File Format:PDF
  • Delivery:Via email within 1~3 business days
Price(USD): $250.00
$243.00
Standard No: GB/T 36474-2018
Document status: VALID
Title in English: Semiconductor integrated circuit—Measuring methods for double data rate 3 synchronous dynamic random access memory(DDR3 SDRAM)
Title in Chinese: 半导体集成电路 第三代双倍数据速率同步动态随机存储器 (DDR3 SDRAM)测试方法
Language: English
File Format: Electronic (PDF)
Delivery: Via email within 1~3 business days
Issued on: 2018-06-07
Implemented on: 2019-01-01
ICS Classification: 31.200-Integrated circuits. Microelectronics
Chinese Classification: L56-Semiconductor integrated circuit
Professional Classification: GB-National Standard
Related Keywords: synchronous dynamic random access memory
double data rate
circuit measuring methods
ddr3 sdram
ddr3 sdramd
Related Topics: Third Generation
tck
Multiplier test
Save three and a half minutes
RAM
Three data testing methods
Ten times the test into
third generation semiconductor
data rate
Double 85 test data
Dual lead data
GBT36474
GB/T 36474-2018
Test method for semiconductor integrated circuit driver
Dynamic conductivity detection
Myoelectric gait acquisition method

《GB/T 36474-2018半导体集成电路 第三代双倍数据速率同步动态随机存储器 (DDR3 SDRAM)测试方法》由TC599(全国集成电路标准化技术委员会)归口,主管部门为工业和信息化部(电子)。


Scope

This standard specifies the method for the third generation double data rate synchronous dynamic random access memory (CDDR3 SDRAMD) of semiconductor integrated circuits (CDDR3 SDRAMD function verification and electrical parameter testing methods. This standard is applicable to the third generation double data rate synchronous dynamic random access memory in the field of semiconductor integrated circuits (DDR3 SDRAMD) functional verification and electrical parameter testing.

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