GB/T 44798-2024 in English
VALIDDesign assurance guidelines for complex integrated circuits
- Issued on:2024-10-26
- Implemented on:2024-10-26
- File Format:PDF
- Delivery:Via email within 5 business days
$301.00
| Standard No: | GB/T 44798-2024 |
| Document status: | VALID |
| Title in English: | Design assurance guidelines for complex integrated circuits |
| Title in Chinese: | 复杂集成电路设计保证指南 |
| Language: | English |
| File Format: | Electronic (PDF) |
| Delivery: | Via email within 5 business days |
| Issued on: | 2024-10-26 |
| Implemented on: | 2024-10-26 |
| ICS Classification: | 31.200-Integrated circuits. Microelectronics |
| Chinese Classification: | L56-Semiconductor integrated circuit |
| Professional Classification: | GB-National Standard |
| Related Keywords: | complex integrated circuits
design assurance guidelines design assurance digital circuit design test verification design |
| Related Topics: | Impurity verification
Including the following aspects: integrated circuit |
《GB/T 44798-2024复杂集成电路设计保证指南》由TC599（全国集成电路标准化技术委员会）归口，主管部门为工业和信息化部（电子）。
Introduction
1. Standard Overview
GB/T44798-2024 "Guidelines for Design Assurance of Complex Integrated Circuits" is a standard document guiding the design process and quality assurance of complex integrated circuits. The standard applies to various integrated circuits that can be programmed and customized by users according to specific applications, and aims to ensure the standardization and reliability of the design process.
2. Comparison of standard frameworks
| Standard dimensions | Technical requirements | Verification methods |
|---|---|---|
| Design process | System requirements analysis, specification definition, digital circuit design, analog circuit design | Phase review and simulation verification |
| Reliability indicators | Operating temperature range, electrostatic discharge sensitivity (ESDS), radiation resistance | Reliability simulation and test verification |
| Design for testability | Scan chain, built-in self-test (BIST), boundary scan cell (BSC) | Automated test vector generation and verification coverage analysis |
3. Core technology evolution analysis
Case: Digital circuit design process optimization
The traditional digital circuit design process includes hardware description language (HDL) input, logic synthesis, physical implementation and simulation verification. In recent years, with the continuous advancement of process nodes, logic synthesis tools have gradually supported more efficient gate-level optimization algorithms, and parasitic parameter extraction and timing analysis techniques in the physical implementation stage have also been continuously improved.
Take Verilog as an example, which is widely used in the design of complex integrated circuits. Through comparative analysis with VHDL, it can be found that Verilog has more advantages in syntax simplicity and parallel processing capabilities, but VHDL performs better in behavioral simulation and system-level modeling.
4. Implementation Suggestions
- Adopt standardized tool chains and processes to ensure the standardization and traceability of the design process.
- Perform a comprehensive reliability analysis in the system requirements phase to avoid rework in the later stages of design.
- Strengthen the collaborative design between digital circuits and analog circuits, and optimize the selection of mixed-signal simulation platforms.
- For the testability design of complex integrated circuits, automatic test pattern generation (ATPG) and built-in self-test (BIST) technologies are preferred.
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