GB/T 35008-2018 in English
VALIDSpecification for serial NOR flash interface
- Issued on:2018-03-15
- Implemented on:2018-08-01
- File Format:PDF
- Delivery:Via email within 5 business days
$476.00
| Standard No: | GB/T 35008-2018 |
| Document status: | VALID |
| Title in English: | Specification for serial NOR flash interface |
| Title in Chinese: | 串行NOR型快闪存储器接口规范 |
| Language: | English |
| File Format: | Electronic (PDF) |
| Delivery: | Via email within 5 business days |
| Issued on: | 2018-03-15 |
| Implemented on: | 2018-08-01 |
| ICS Classification: | 31.200-Integrated circuits. Microelectronics |
| Chinese Classification: | L56-Semiconductor integrated circuit |
| Professional Classification: | GB-National Standard |
| Related Topics: | memory
internal memory fast+ nor+ flash memory flash NOR Flash type art serial quick flash GBT35008 GB/T 35008-2018 Liquid flash industry |
《GB/T 35008-2018串行NOR型快闪存储器接口规范》由TC599（全国集成电路标准化技术委员会）归口，主管部门为工业和信息化部（电子）。
Introduction
Analysis of the core content of the standard
GB/T 35008-2018 is China's first national standard for 24-bit address serial NOR flash memory, which was formulated by GigaDevice and other companies. The standard unified the technical specifications of physical interface, instruction system and functional parameters for the first time.
Interface Architecture Comparison
| Mode Type | Signal Port | Transmission Rate | Function Support | Enabled Method |
|---|---|---|---|---|
| Single Port | SCLK, CS#, SI, SO | 1x | HOLD#/WP# | Default |
| Dual Port | SCLK, CS#, SI/SIO0, SO/SIO1 | 2x | HOLD#/WP# | Instruction Switching |
| Four ports | 6 signal ports | 4x | Disable protection function | Set QE bit |
Key technological innovations
1. Dynamic mode switching mechanism
Seamless switching between single/quad port modes is achieved through the QE bit of the status register, and dynamic adjustment of the transmission rate is achieved in conjunction with the instruction set.
2. Security Protection System
- Three-level protection: software protection (BP bit), hardware protection (WP# pin), self-destruct instruction
- Block protection granularity is up to 4KB, supporting 63 protection combinations (see Table A.1)
Detailed Explanation of Instruction System
Typical Instruction Timing Characteristics
| Instruction Type | Operation Code | Clock Edge | Data Bit Width | Typical Application |
|---|---|---|---|---|
| Fast Read | 0BH/EBH | Falling Edge Output | 1/4bit | High-speed Data Read |
| Page Programming | 02H/32H | Rising Edge Latching | 8bit | 256 Bytes Write |
| Sector Erase | 20H | - | - | 4KB Erase |
Innovative Instruction Cases
Four-port Word Read Instruction (E7H): Reduce redundant clocks by optimizing address alignment (A0=0), and improve reading efficiency by 20% compared to EBH instructions.
Self-destruction instruction sequence: A5H-FAH-A5H-0AH-10H five-segment instruction ensures that the operation is irreversible and meets military-grade security requirements.
Implementation Suggestions
- During design, give priority to verifying the WIP bit of the status register to ensure compliance with the operation timing
- In the four-port mode, it is necessary to pay attention to the mutual exclusion of the functions of the QE bit and WP#/HOLD#
- The parameter table should include a statement of support for modes such as 1-1-4/1-4-4
The implementation of this standard requires the matching of "Semiconductor Device Digital Integrated Circuit" GB/T 17574 for compatibility verification.
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