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GB/T 36479-2018 in English

GB/T 36479-2018 in English

VALID

Integrated circuits—Test methods for column grid array

  • Issued on:2018-06-07
  • Implemented on:2019-01-01
  • File Format:PDF
  • Delivery:Via email within 5 business days
Price(USD): $310.00
$301.00
Standard No: GB/T 36479-2018
Document status: VALID
Title in English: Integrated circuits—Test methods for column grid array
Title in Chinese: 集成电路 焊柱阵列试验方法
Language: English
File Format: Electronic (PDF)
Delivery: Via email within 5 business days
Issued on: 2018-06-07
Implemented on: 2019-01-01
Professional Classification: GB-National Standard
Related Keywords: circuits test methods
integrated circuit solder pillar arrays
solder column
integrated circuits
test methods
Related Topics: column english
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《GB/T 36479-2018集成电路 焊柱阵列试验方法》由TC599(全国集成电路标准化技术委员会)归口,主管部门为工业和信息化部(电子)。


Introduction

Standard Overview

GB/T 36479-2018 "Test Method for Integrated Circuit Solder Pillar Arrays" is a method standard for testing integrated circuits in the form of solder pillar array (CGA) packaging. This standard specifies a variety of test indicators such as coplanarity, position, solderability, pull-off force, shear force and fatigue of solder pillar arrays, and is applicable to different types of solder pillars such as high-lead solder pillars and micro-coil solder pillars.

Detailed technical requirements

Project Test content Key indicators
Coplanarity Measure the maximum deviation from the top of the solder column to the reference plane Maximum allowable deviation: ≤150μm
Position Determine the deviation between the center of the solder column and the theoretical position Depending on the pitch, the maximum allowable deviation range is 80-150μm
Solderability Evaluate the soldering performance of solder pillars under reflow conditions Sn63Pb37 or lead-free solder is recommended, with wettability ≥ 95%

Background of standard formulation and technological evolution

With the development of integrated circuit packaging technology, solder pillar arrays, as a high-performance connection method, have been widely used in high-end chip packaging. This standard is formulated based on military standards such as GJB548B-2005, and the test methods are optimized and supplemented in combination with the needs of the civilian market.

Implementation recommendations

  • In mass production, it is recommended to use automated equipment for coplanarity and position detection to improve efficiency and accuracy.
  • For high-reliability applications, it is recommended to add fatigue test items to evaluate the durability of solder pillars in long-term use.
  • When selecting test parameters, the test conditions should be adjusted according to the pitch and material properties of the specific device to ensure the validity of the results.

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