GB/T 43366-2023 in English
VALIDGeneral specification for discrete semiconductor devices of space application
- Issued on:2023-11-27
- Implemented on:2024-03-01
- File Format:PDF
- Delivery:Via email within 5 business days
$650.00
《GB/T 43366-2023宇航用半导体分立器件通用规范》由TC425(全国宇航技术及其应用标准化技术委员会)归口,TC425SC2(全国宇航技术及其应用标准化技术委员会宇航电子分会)执行,主管部门为国家标准委。
Introduction
Analysis of the core framework of the standard
| Technical dimensions | Grade A devices | Grade B devices | Grade C devices |
|---|---|---|---|
| Quality assurance level | Aerospace key systems | General aerospace systems | Non-critical loads |
| High temperature life test (h) | 1000 | 340 | 48 |
| Number of temperature cycles | 500 | 25 | 20 |
Key Technical Requirements
4.2 Quality Assurance Level System
The standard establishes a three-level quality assurance system: Level A is applicable to key systems such as long-life satellites (with the highest test severity), Level B is used for general spacecraft systems, and Level C is applicable to short-term mission payloads.
- Grade A needs to pass 1000 hours of 240℃ assessment
- Grade B requires 160 hours of testing under the same conditions
- Grade C only needs 48 hours of verification
4.5 Identification System Specifications
Unique seven-segment identification code:
Example: A R-IV QX-1002 means:
- A - Quality assurance grade A
- R - Total dose resistance 103Gy(Si)
- IV - Single event effect threshold ≥75MeV·cm2/mg
- QX-1002 - Device model
- Metalization layer defects at the oxide layer step
- Metal strip cross-sectional area loss rate <50%
- Zero tolerance for unattached defects in the bonding area
- Grade A devices must provide chip identification reports
- 22 pieces of sampling passed the high temperature life test with zero failures
- The change in key parameters Δ needs to be continuously monitored
- Incoming inspection: Check the integrity of the identification system
- DPA analysis: Destructive verification of 3-5 pieces per batch
- Batch release: Comprehensive judgment based on 6.5 basket selection data
5.9 SEM inspection standards
SEM resolution is required to be ≤10nm, and the key inspections are:
Implementation suggestions
Supply chain management
Outsourced chips need to be evaluated according to Table 4 for wafer batches:
Acceptance process optimization
It is recommended to adopt a three-level acceptance strategy:

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