GB/T 4937.26-2023 in English

The standard clearly requires that the HBM test system must include:

• Digital oscilloscope: vertical resolution ≥8bit, sampling rate ≥1GSa/s
• Current sensor: rise time <1ns, bandwidth ≥200MHz
• HBM simulator: parasitic capacitance <5pF, in line with the circuit topology in Figure 1

Appendix B specifically emphasizes the need to test the parasitic characteristics of the equipment, including the trailing edge pulse (<4μA@4kV) and the pre-pulse voltage (<5% of the set value)

The standard provides two pin combination schemes:

1. Preferred scheme (Table 2): Based on the interconnection relationship of the power pin group, reduce unnecessary test combinations
2. Alternative scheme (Table 3): Full pin matrix test, suitable for situations where design information is incomplete

Appendix C uses a typical case to illustrate: For multi-power domain devices, the scheme in Table 2 can reduce the test volume by 62%

Main improvements compared to the old version of the standard:

• Added two-pin HBM test equipment specification (3.28)
• Refined the definition of coupled non-power pin pairs (Appendix D)
• Introduced the sampling method for I/O pins with the same name (Appendix E)

These changes reflect the ESD testing challenges brought about by the high integration of modern semiconductor devices, especially for:

• Parasite parameter control of 3D packaged devices
• Differential pair ESD protection of high-speed interfaces
• Improved test efficiency of large-scale I/O arrays

Laboratory Construction Guide:

1. Give priority to test equipment that supports low parasitic verification in Appendix B.4
2. Establish a daily waveform inspection system (Clause 5.5)
3. Increase the frequency of 500Ω load testing for high-frequency devices

Test process optimization:

• Use Table 2 + I/O sampling combination with the same name for devices with >100 pins
• Power supply pin group testing using a unipolar simplified flow (6.6.2.3)
• Developing automated test scripts using the sample program in Appendix C